A continuing goal in semiconductor processing is to reduce the size of individual electronic components, and to thereby enable smaller and denser integrated circuitry. For instance, it can be desired to form memory circuitry (such as DRAM, NAND memory, etc.) to increasingly higher levels of integration.
A concept commonly referred to as “pitch” can be used to quantify the density of an integrated circuit pattern. Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern. Feature size limitations of a lithographic technique can set a minimum pitch that can be obtained from the lithographic technique.
Lithographic processes, such as photolithography, are commonly utilized during semiconductor processing for fabricating integrated structures. Lithographic processes have minimum capable feature sizes, F, which are the smallest feature sizes that can be reasonably formed with the processes. For instance, photolithography may be limited by factors such as optics and radiation wavelength.
Pitch multiplication, such as pitch-doubling, is a method for extending the capabilities of lithographic techniques beyond their minimum pitches. Pitch multiplication may involve forming sub-lithographic features (i.e., features narrower than minimum lithographic resolution) by depositing a material to have a thickness which is less than that of the minimum capable lithographic feature size, F. The material may be anisotropically etched to form the sub-lithographic features. The sub-lithographic features may then be used for integrated circuit fabrication to create higher density circuit patterns than can be achieved with conventional lithographic processing.
It is desired to develop new methods of patterning which are suitable for fabrication of highly-integrated structures.